1. Field of the Invention
The present invention relates to a mixed-voltage semiconductor integrated circuit, and in particular to the transfer of signals between circuit blocks operating at different voltage levels.
2. Description of the Related Art
Large-scale integrated circuits are at risk of two general types of internal electrostatic destruction (ESD). One type, which was formerly the main type, damages pn junctions by creating parasitic bipolar transistors and parasitic diodes. The other type, which has become more frequent as mixed-voltage designs have become increasingly common, damages the gate oxide films of transistors in the receiving buffers in mixed-voltage interfaces.
ESD protection can be provided by, for example, simple diode circuits that shunt current from input and output signal lines to the power supply or ground when the voltages on the signal lines become abnormally high or low. ESD protection circuits of this type are normally provided for all external input and output signal terminals. More robust ESD protection circuits that can shunt current between power-supply and ground terminals are also commonly present. Electrostatic discharges at the external power or ground terminals of a mixed-voltage integrated circuit, however, can produce surges that reach the buffers that transfer signals between different voltage domains in the core area before the power-to-ground protection circuits have time to operate. This is especially true in devices with highly conductive metal wiring and salicided gate electrode lines.
To improve the ESD immunity of mixed-voltage circuits, non-salicided structures are sometimes used in active regions between gate contacts, but the resulting added resistive component delays response to surges, and may actually promote internal destruction.
The best type of ESD protection for an internal mixed-voltage interface is to provide a separate ESD protection circuit on each interface signal line, as illustrated in FIG. 1. The device in this drawing has one core domain, including a central processing unit (CPU), that operates at a comparatively high voltage level (E1) and another core domain, including a random-access memory (RAM), that operates at a lower voltage level (E2). The E1 power supply can be switched off to save power while the E2 power supply remains switched on to retain data. A total of thirty-nine signal lines, including one write enable (we) signal line, one read enable (re) signal line, one chip enable (ce) signal line, four address (adr) signal lines, sixteen write data (wdata) signal lines, and sixteen read data (rdata) signal lines, are used to transfer data over sixteen-bit-wide data paths between the two voltage domains. Each one of the thirty-nine signal lines has a separate ESD protection circuit. FIG. 2 illustrates the structure of an ESD protection circuit in the E2 domain; the structure includes transistors p0 and n0 that function as diodes, and a resistor r0.
A problem with this type of mixed-voltage interface is that the area occupied by the ESD protection circuits increases in proportion to the number of signal lines that cross boundaries between different voltage blocks. Each ESD protection circuit occupies a space of about two thousand to three thousand square micrometers (2000-3000 μm2), so the total area occupied by the ESD protection circuits in FIG. 1, for example, is on the order of 0.12 square millimeter (0.12 mm2=0.003 mm2×40). This is a not insignificant fraction of the total area of a large-scale integrated circuit chip.
Integrated circuits in which the number of ESD protection circuits is reduced by providing a protection circuit between each power supply terminal and a common node in place of a protection circuit for each internal signal line are also known (see, for example, Japanese Patent Application Publication No. H5-299598), but the protection afforded by this scheme is less robust than in FIG. 1.